1. Field of the Invention
The present invention relates to an electrostatic discharge (hereinafter abbreviated as ESD) protection circuit, an ESD protection semiconductor device, and a layout structure of an ESD protection semiconductor device, and more particularly, to an ESD protection circuit including an ESD protection semiconductor device and a layout structure of the ESD protection semiconductor device.
2. Description of the Prior Art
With the advancement of technology, the development of semiconductor process is ongoing. A modern chip is therefore allowed to have a plurality of various electronic circuits configured within. For example, the integrated circuits (hereinafter abbreviated as ICs) integrated in the chip(s) can be divided into core circuits and input/output (hereinafter abbreviated as I/O) circuits, and the core circuits and the I/O circuits are respectively driven by different power supply sources with different voltages. And for receiving the externally provided power, pads for the core circuits and the I/O circuits are required.
However, it is found that electrostatic charges are easily transferred to the inner circuits in the chip by those pads during processes such as manufacturing, testing, packaging, and delivering, etc. The electrostatic charges impact and damage the inner circuits in the chip(s), and this unwanted condition is named electrostatic discharge (ESD). As products based on ICs become more delicate, they also become more vulnerable to the impacts from external environment. And thus, it is assumed that ESD is a constant threat to the modern electronics. As a countermeasure against to the ESD issue, there have been proposed ESD protection circuits/devices. Typically, during a normal IC operation, the ESD protection device is turned off. However when an ESD event occurs, the ESD protection device must be quickly triggered, so that the ESD current is immediately bypassed from the inner circuit.
Typically, when a voltage across the ESD protection device/circuit is higher than trigger voltage (Vt1), snapback breakdown occurs and the voltage is clamped. In other words, when snapback breakdown occurs, the voltage across the circuit drops down to the holding voltage. It is found the low holding voltage leads better robustness. However, a problem arises when the holding voltage is lower than the operating voltage (Vdd) at which the ESD protection device/circuit operates: it is easily latched-up and thus cannot provide protection to the internal circuit. In order to solve the latch-up issue, a stacked ESD device has been introduced. Despite having a relatively high holding voltage, the stacked ESD device is formed by a plurality of gate-grounded n-type metal-oxide-semiconductor (nMOS) transistors electrically connected in series, thereby requiring larger layout area.